一般注記 |
Layout design and verification, 1986: CIP t.p. (T. Ohtsuki; Dept. of Electronics and Communication Engineering, School of Science and Engineering, Waseda Univ., Toyko, Japan) data sheet (Ohtsuki, Tatsuo; b. 6/16/40) Zenkoku daigaku shokuin, 1985: p. 869 (Ōtsuki Tatsuo; b. Shōwa 15; prof., Rikō Gakubu, Waseda Daigaku) EDSRC:回路とレイアウト / 渡辺誠 [ほか著](岩波書店, 1985.1)
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