REDUCED INSTRUCTION SET COMPUTER ARCHITECTURES FOR VLSI
Reduced instruction set computer architectures for VLSI / Manolis G.H. Katevenis
| Material Type | Books |
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| Publisher | Cambridge, Mass. : MIT Press |
| Year | c1985 |
| Language | English |
| Size | 215 p. ; 24 cm |
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| Location | Volume | Call No. | Barcode No. | Status | ISBN | Media type | Restriction | Request Memo | Reserve |
|---|---|---|---|---|---|---|---|---|---|
| 1F書庫3-洋書 |
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549.7/KA85 | 002064388 | 0262111039 | 図書 |
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| Notes | Originally presented as author's thesis (Ph.D.)--University of California, Berkeley, 1983 Bibliography: p. [201]-207 Includes index |
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| Authors | *Katevenis, Manolis G. H. |
| Subjects | LCSH:Computer architecture LCSH:Integrated circuits -- Very large scale integration |
| Classification | LCC:QA76.9.A73 DC19:621.3819/5835 |
| ID | 1000069392 |
| ISBN | 0262111039 |
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